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[hmac,dv] Fix fifo_empty interrupt #25683

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[hmac,dv] Fix fifo_empty interrupt #25683

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@martin-velay martin-velay commented Dec 17, 2024 •
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  • linked to issue [hmac,dv] intr_state TB issue #24691
  • where the interrupt state for fifo_empty field from the RAL against the RTL were not matching. This was the case when all the empty conditions were filled but at the same time a full is coming. It was just a matter of changing the condition order in the TB.
  • fix also FIFO depth status by allowing +1 of tolerance as this is not super critical to be cycle accurate.

@martin-velay
[hmac,dv] Fix fifo_empty interrupt
0c2c4c1 
- linked to issue lowRISC#24691
- where the interrupt state for fifo_empty field from the RAL against
the RTL were not matching. This was the case when all the empty
conditions were filled but at the same time a full is coming. It was
just a matter of changing the condition order in the TB.
- fix also FIFO depth status by allowing +1 of tolerance as this
is not super critical to be cycle accurate.

Signed-off-by: Martin Velay <[email protected]>
@martin-velay martin-velay marked this pull request as ready for review December 20, 2024 14:11
@martin-velay martin-velay requested a review from a team as a code owner December 20, 2024 14:11
@martin-velay martin-velay removed the request for review from a team December 20, 2024 14:12
@martin-velay martin-velay self-assigned this Dec 20, 2024
vogelpi
vogelpi approved these changes Dec 21, 2024
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This looks good to me, thanks @martin-velay !

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@vogelpi vogelpi vogelpi approved these changes

@rswarbrick rswarbrick Awaiting requested review from rswarbrick

@marcelocarvalhoLowRisc marcelocarvalhoLowRisc Awaiting requested review from marcelocarvalhoLowRisc

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